1. Field of the Invention
This invention relates to a design and simulation method and apparatus for simulating the behavior of systems such as electronic circuits. In particular, the invention provides a method and apparatus for simulating the behavior of an electronic circuit which is being modified in an incremental fashion.
2. Description of the Prior Art
Traditional approaches to the simulation of electronic hardware have been characterized by a loose coupling of schematic capture and simulation tools. This loose coupling has been implemented as an ASCII or binary netlist file which is created by a stand-alone schematic capture system. A stand-alone simulator processes this netlist file as an input during initial startup. In this approach, the netlist file represents a fully expanded circuit description with all schematic hierarchy removed prior to generation of the netlist file. Such computer-aided design tools include those sold by Silvar-Lisco (the Helix System).
In the development of an electronic design, a user of such systems frequently makes incremental changes to the design in order to evaluate alternative designs. A user is forced through the following sequence of operations when making such incremental changes to an electronic design when using the above systems:
1. A schematic editor is started. PA1 2. Changes to the schematic are made in the editor. PA1 3. The schematic is checked for errors. PA1 4. The hierarchy of the schematic is expanded/flattened. PA1 5. A netlist file suitable for simulation is generated. PA1 6. The simulator is started. PA1 7. The simulation is performed and the results are viewed.
The computer processing times to generate the netlist file can be significant (often measured in minutes or hours), and this processing is required for every incremental change made to the electronic design. Further, the simulator must be restarted for each change. As a consequence, the design turn-around time (the time it takes to make an incremental change and proceed to viewing simulation results) often dominates the overall productivity of the user.
Certain systems have been developed (e.g., the Mentor Graphic "QuickSim" simulator) which provide incremental "patching" capabilities during simulation. The ability to change device parameter values during simulation, freeze signal values, change min/max timing values, and make simple patches to the netlist has previously been possible. Such patches have been limited to replacement of gate level components where the number and direction of pins on the replacement part exactly match the component to be replaced and changes are permitted only at the leaf level of hierarchy. Systems which permit patching include "Quicksim" by Mentor Graphics.
From the above it is seen that an improved method and apparatus for performing computer aided design is desired, especially one for use in performing/making incremental changes in the design of an electronic circuit.